Speedup and Power Scaling Models for Heterogeneous Many-Core Systems

Power-Aware Core Management Scheme for Heterogeneous Many-Core Architecture

OF THE THESIS Power-Aware Core Management Scheme for Heterogeneous Many-Core Architecture By Myoung-Seo Kim Master of Science in Computer Engineering University of California, Irvine, 2015 Professor Jean-Luc Gaudiot, Chair The main challenge in designing the future heterogeneous many-core architecture on the same chip is to provide a solution that has low power consumption, in addition to trade...

An Execution Model and Runtime For Heterogeneous Many-Core Systems

SPAP: A Programming Language for Heterogeneous Many-Core Systems

We present SPAP (Same Program for All Processors), a containerbased programming language for heterogeneous many-core systems. SPAP abstracts away processor-specific concurrency and performance concerns using containers. Each SPAP container is a high level primitive with an STL-like interface. The programmervisible behavior of the container is consistent with its sequential counterpart, which en...

Extended Power and Energy Normalized Performance Models for Many-Core Systems

Continued technology scaling in VLSI has enabled more and more computation cores to be integrated in the same chip. This has facilitated the parallelization of processing and the increase of performance whilst keeping energy consumption at reasonable levels. To study the potential improvement of performance in such many core systems, three existing models have been popular in both the research ...

Virtualizing Heterogeneous Many-core Platforms

Introduction. The relentless progress of Moore’s Law has periodically inspired major innovations – both in hardware and software – at specific points in time to keep performance growth on pace with transistor density. Industry has reached another such point as it encounters intellectual and engineering challenges in the form of power dissipation, processor-memory performance gap, limits to inst...